Date	: Mar 6th, 2002
		Category	: CPU
		Manufacturer	: VIA
		Author	: Jin-Wei Tioh

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This achieved a number of things. Since the size of the transistors in the chip, the required voltage and current (and thus power, P = VI) were reduced. The decrease in power dissipation also translates to a decrease in heat energy released. Lastly, since less silicon wafer is needed to produce each chip, the cost price of each chip is also decreased. The C3 has a miniscule die size of just 52mm^2, about half that of the Duron (Spitfire), Pentium III (Coppermine) and Celeron (Coppermine128). Power dissipation is also a measly 10.35W at 1.6V, roughly less than half that of all AMD and Intel CPUs.

However the price for this is a decrease in complexity, with the C3 having a generally simpler internal architechture. The 2 64KB L1 caches from the original Samuel core remain, with a new 64KB L2 cache added to the Samuel2. The L2 cache is an exclusive cache, instead of the more conventional inclusive cache architechture. The Pentium III (Coppermine) and the Celeron (Coppermine128) both implement an inclusive L2 cache, meaning that all of the data stored in their L1 cache is duplicated in their L2 cache.

An exclusive cache is the anti-matter of an inclusive cache, not duplicating L1 cache data in the L2 cache. The L2 cache now contains only the copy-back cache blocks, ie. blocks that are designated to be written back to the memory sub-system. What does this mumbo-jumbo mean? Data that doesn't fit in a CPU's L1 cache would normally go back into the main system memory if no L2 cache was present, a bad thing considering that system memory has a higher latency (waiting period) than cache memory. So although the C3 only has a 64KB L2 cache, it does not contain a copy of the L1 cache, giving an effective total of 192KB of frequently used data (128KB L1 + 64KB L2). The Celeron, having an inclusive L2 cache, duplicates the L1 cache's contents. Because of this, the Celeron actually only has 128KB of cache to store frequently used data.

Another aspect of L2 cache memory is its associativity. The C3 only has a 4-way set associative L2 cache, on par with the Celeron. By comparison, the Pentium III's is 8-way, and both the Duron's and Thunderbird's are 16-way. This is one of the drawbacks of the C3's and Celeron's smaller die sizes. A higher associativity allows for a higher hit rate for the L2 cache, bringing about obvious performance benefits.

VIA did not implement OOO (out-of-order) instruction execution on the C3. OOO execution increases performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. OOO execution helps to maximize CPU efficiency and throughput by keeping the CPU's instruction pipelines full by executing instructions "out of order". While the lack of this architechtural feature will certainly hurt the C3's performance, it is a necessary sacrifice to achieve its small die size.

Lastly, the VIA C3 runs on the same GTL+ (gunning transistor logic) bus as the Pentium III / Celeron CPUs, meaning that the C3 is electrically compatible with these Intel CPUs. Thus, it is no surprise that the C3 uses the same socket format as the Pentium III / Celeron. The following table is a technical summary of several processors, including the original Samuel-based C3.

Socket-370 CPU Technical Comparison

	VIA Cyrix III	VIA C3	Intel Celeron	Intel Pentium III
Core Name	Samuel	Samuel2	Coppermine128	Coppermine
Clock Speed	500 - 667MHz	667 - ?MHz	533 - 1000MHz	500 - 1130MHz
L1 Cache	128KB	128KB	32KB	32KB
L2 Cache	N/A	64KB	128KB	256KB
L2 Cache Speed	N/A	Core Clock	Core Clock	Core Clock
L2 Cache Type	N/A	Exclusive	Inclusive	Inclusive
SIMD Support	MMX, 3DNow!	MMX, 3DNow!	MMX, SSE	MMX, SSE
Electrical Bus	100 - 133MHz GTL+	100 - 133MHz GTL+	66 - 100MHz GTL+	100 - 133MHz GTL+
Die Size	75mm^2	52mm^2	106mm^2	106mm^2
Manufacturing Process	0.18µ	0.15µ	0.18µ	0.18µ

This pretty much covers the technical aspect of the new Samuel2-based C3. How do they translate into real-world performance? Let's find out.

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